Variable bitspace architecture with variable precision processor

Sukemi, Anak Agung Putri Ratna, Harry Sudibiyo

Research output: Contribution to journalArticlepeer-review

Abstract

This research is purposed to increase computer function into a time driven to support real time system. This purposed would the processor can work according to determined time variable and can work optimally in a certained deadline. The first approachment to design some of processor that has a different bit space 64, 32, 16 and 8 bits. Each processor will be separated by selector/arbiter priority of a task. In addition, the design of the above processors are designed as a counter with varying levels of accuracy (variable precision computing). The selection is also done by using statistical control in the task are observed by the appearance of controller mounted on the front of the architecture bitspace the second approach above. The last approach to 'add' certainty in the form of interval arithmetic precision cutting task that can be the upper bound and lower bound of the area (bounds). These four approachment can be structured orthogonally or stand alone into a processor/several processors by introducing a new classifier that serves as a selector or a task arbiter. The result from the four approaches proves that the processor is strutured with different bitspace able to work optimally on a variable time and time deadlines are fast, and accurate completion of tasks in support of real time.

Original languageEnglish
Pages (from-to)534-537
Number of pages4
JournalAdvanced Science Letters
Volume20
Issue number2
DOIs
Publication statusPublished - 1 Feb 2014

Keywords

  • Interval arithmetic
  • Task arbiter
  • Time driven
  • Variable precision computing

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