Rijndael cipher optimization using low complexity serial multiplier based on Karatsuba technology

Improving efficiency of Galois Field (GF) operators has become attention to researchers, either by reducing time or space in FPGA implementation. This paper shows that speed improvement could be achieved by applying Karatsuba-based serial multiplication in Rijndael Cipher. Throughput improvement is gained from overall performance of ciphering process instead of improvement over any single arithmetic operator. Cipher algorithm was implemented in two FPGA platforms: Xilinx and Altium and then compare the throughput obtained by every combination of processing structure and GF representation basis. The experiment shows that 20% throughput improvement is accumulated by 83% time efficiency and automated synthesis optimization due to constant variable in polynomial multiplications. This paper demonstrates significant efforts that has been put to evaluate application performance by applying all best operators versus optimal configuration. The result gives us a new insight in performance evaluation technique specifically for GF based applications.