Performance improvement of digital phase locked loop algorithm using all pass filter and low pass filter for grid connected inverter reference

Feri Yusivar, Y. Syaifuddin, A. N. Rahman

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

Digital Phase Locked Loop (PLL) is an algorithm that is used to detect the phase, frequency, and amplitude of a signal. The output of digital PLL algorithm can be used as synchronization reference for grid connected inverter. A digital PLL algorithm is very popular to be used since its structure is very simple and it has high accuracy. However, the output of digital PLL is not stable if the input reference frequency is shifted from the pre-defined fundamental frequency and that condition will result an oscillation in digital PLL output. In this paper, an algorithm modification is employed using low pass filter and all pass filter to improve the digital PLL output response under various condition. All simulation results will be shown and compared to the conventional algorithm.

Original languageEnglish
Title of host publicationMachinery Electronics and Control Engineering II
Pages1274-1278
Number of pages5
DOIs
Publication statusPublished - 29 Apr 2013
Event2012 2nd International Conference on Machinery Electronics and Control Engineering, ICMECE 2012 - Jinan, Shandong, China
Duration: 29 Dec 201230 Dec 2012

Publication series

NameApplied Mechanics and Materials
Volume313-314
ISSN (Print)1660-9336
ISSN (Electronic)1662-7482

Conference

Conference2012 2nd International Conference on Machinery Electronics and Control Engineering, ICMECE 2012
Country/TerritoryChina
CityJinan, Shandong
Period29/12/1230/12/12

Keywords

  • All pass filter
  • Low pass filter
  • PLL
  • Synchronization

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