Digital Phase Locked Loop (PLL) is an algorithm that is used to detect the phase, frequency, and amplitude of a signal. The output of digital PLL algorithm can be used as synchronization reference for grid connected inverter. A digital PLL algorithm is very popular to be used since its structure is very simple and it has high accuracy. However, the output of digital PLL is not stable if the input reference frequency is shifted from the pre-defined fundamental frequency and that condition will result an oscillation in digital PLL output. In this paper, an algorithm modification is employed using low pass filter and all pass filter to improve the digital PLL output response under various condition. All simulation results will be shown and compared to the conventional algorithm.