Reed Solomon Codec has been optimized by applying a new bit-level serial multiplier in the computation process of RS(15,11) 4-bit. The new multiplier took advantage of partial decoding process with fewer delay, and hence able to proceed in higher cycle rate. The RS Codec involves dominant multiplications which have been replaced by Fully Serial In Parallel Out (FSIPO) multiplier and implemented in Xilinx and Altium FPGA Board. The experiment results in throughput improvement of 11% and time efficiency of 23% in addition to automatic optimization by the synthesis tools due to the existence of constant variables in polynomial multiplications. This paper confirms that the most optimal RS Codec can be achieved by selecting the best configuration of GF arithmetic operators, each of which does not necessarily the best variant. A new perspective of GF application performance evaluation has been endorsed by the results reported in this paper.