@inproceedings{26d1681e19ec4b6bbb80d9a79482a91f,
title = "New Polynomial Based Bit-Level Serial GF(2m) Multiplier for RS(15,11) 4-bit Codec Optimization",
abstract = "Reed Solomon Codec has been optimized by applying a new bit-level serial multiplier in the computation process of RS(15,11) 4-bit. The new multiplier took advantage of partial decoding process with fewer delay, and hence able to proceed in higher cycle rate. The RS Codec involves dominant multiplications which have been replaced by Fully Serial In Parallel Out (FSIPO) multiplier and implemented in Xilinx and Altium FPGA Board. The experiment results in throughput improvement of 11% and time efficiency of 23% in addition to automatic optimization by the synthesis tools due to the existence of constant variables in polynomial multiplications. This paper confirms that the most optimal RS Codec can be achieved by selecting the best configuration of GF arithmetic operators, each of which does not necessarily the best variant. A new perspective of GF application performance evaluation has been endorsed by the results reported in this paper.",
keywords = "FPGA., Galos Field, Polynomial Basis, Reed Solomon",
author = "Petrus Mursanto and Nugroho, {R. Dimas}",
note = "Funding Information: This work was supported by funding from University Grant for Internationally Indexed Publication of Students' Final Project (Hibah PITTA) Contract No: 414/UN2.R3.1/HKP.05.00/2017, administered by the Directorate of Research and Community Engagement (DRPM), Universitas Indonesia Funding Information: This work was supported by funding from University Grant for Internationally Indexed Publication of Students{\textquoteright} Final Project (Hibah PITTA) Contract No: 414/UN2.R3.1/HKP.05.00/2017, administered by the Directorate of Research and Community Engagement (DRPM), Universitas Indonesia. Funding Information: Part of the research reported in this paper is based upon work supported by European Union Project VN/Asia-Link/001 (79754). The author would like to thank Prof. R.G. Spallek and Mr. J{\"o}rg Schneider for providing tools and facilities in the Professur f{\"u}r VLSI-Entwurfssysteme, Diagnostik und Architektur, Technische Universit{\"a}t Dresden, Germany. Publisher Copyright: {\textcopyright} 2018 IEEE.; 2018 International Workshop on Big Data and Information Security, IWBIS 2018 ; Conference date: 12-05-2018 Through 13-05-2018",
year = "2018",
month = sep,
day = "24",
doi = "10.1109/IWBIS.2018.8471694",
language = "English",
series = "2018 International Workshop on Big Data and Information Security, IWBIS 2018",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
pages = "107--112",
booktitle = "2018 International Workshop on Big Data and Information Security, IWBIS 2018",
address = "United States",
}