New Polynomial Based Bit-Level Serial GF(2m) Multiplier for RS(15,11) 4-bit Codec Optimization

Petrus Mursanto, R. Dimas Nugroho

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

Reed Solomon Codec has been optimized by applying a new bit-level serial multiplier in the computation process of RS(15,11) 4-bit. The new multiplier took advantage of partial decoding process with fewer delay, and hence able to proceed in higher cycle rate. The RS Codec involves dominant multiplications which have been replaced by Fully Serial In Parallel Out (FSIPO) multiplier and implemented in Xilinx and Altium FPGA Board. The experiment results in throughput improvement of 11% and time efficiency of 23% in addition to automatic optimization by the synthesis tools due to the existence of constant variables in polynomial multiplications. This paper confirms that the most optimal RS Codec can be achieved by selecting the best configuration of GF arithmetic operators, each of which does not necessarily the best variant. A new perspective of GF application performance evaluation has been endorsed by the results reported in this paper.

Original languageEnglish
Title of host publication2018 International Workshop on Big Data and Information Security, IWBIS 2018
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages107-112
Number of pages6
ISBN (Electronic)9781538655252
DOIs
Publication statusPublished - 24 Sep 2018
Event2018 International Workshop on Big Data and Information Security, IWBIS 2018 - Balai Kartini, Jakarta, Indonesia
Duration: 12 May 201813 May 2018

Publication series

Name2018 International Workshop on Big Data and Information Security, IWBIS 2018

Conference

Conference2018 International Workshop on Big Data and Information Security, IWBIS 2018
CountryIndonesia
CityBalai Kartini, Jakarta
Period12/05/1813/05/18

Keywords

  • FPGA.
  • Galos Field
  • Polynomial Basis
  • Reed Solomon

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