Incorporating different bitspaces to create a variable precision processor

A processor built with timely precise variable feedback/input or a time-driven processor is expected to work optimally on a specified time limit, although this has not been true for computer architecture in general. The initial approach will be to sort out or even cut off some part of both mandatory and optional tasks from a scheduler. The results of this approach results in a processor that has a separator/trimmer priority of a task. The second approach is to design a processor that has the ability as a counter with varying levels of accuracy (precision variable computing). The final approach is done by ‘adding’ the certainty of precision in the form of interval arithmetic which is able to cut the data/task. The cuts are created in the form of upper and lower limits of the area (bounds). All three approaches can be built into a prototype orthogonal processor that has a bit width that varies (4, 8, 16, 32 and 64 bit) by adding a selector as the bit width of the optimal classifier to yield optimal time computation. The end result of the representation of the arithmetic units in the FPGA simulator shows that the sub-units of arithmetic adder 4, 8, 16, 32 and 64 bits are orthogonally designed to the selector and collector to provide optimization of computation execution time by 4.53% compared to the one that does not use a selector and collector.