Reed Solomon (RS) codes is a mechanism to detect and correct burst of errors in data transmission and storage systems. It provides a solid introduction to foundation mathematical concept of Galois Field algebra and its application. With the development of digital hardware technology, the RS concepts were brought into reality, i.e. the implementation of RS codec chips. This paper presents the development steps of a generic RS encoder using VHDL. The encoder is able to handle generic width of data, variable length of information, number of error as well as variable form of primitive polynomial and generator polynomial used in the system. The design has been implemented for FPGA chip Xilinx XC3S200-5FT256 and has a better performance than commercially available equivalent encoder.