Block and booth floating point number multiplication algorithms in FPGA's generalized learning vector quantization implementation

Yulistiyan Wardhana, H. S. Putra, S. I. Sakinah, Wisnu Jatmiko, Petrus Mursanto, Prahesa Kusuma Setia

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Nowadays, smart devices have been rapidly developed. Most of them are just sensors and actuators without independent computation ability. The devices computation would be done in a device coordinator which need communication time between them. It makes the devices can't respond its input in the right time. Independent computation ability is needed by smart devices. Yet, its implementation has limitation in resource usage and accuracy. One of the problem for the devices accuracy is its number representation for its learning implementation. In this research we propose block and booth floating point number implementation to increase smart devices accuracy with their resource usage comparison. The research resulted FPGA components which could improve previous implemented FPGA algorithm accuracy by 17 % with two alternatives: component with minimal time consumption or component with minimal resource consumption.

Original languageEnglish
Title of host publicationProceedings - WBIS 2017
Subtitle of host publication2017 International Workshop on Big Data and Information Security
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages69-75
Number of pages7
ISBN (Electronic)9781538620380
DOIs
Publication statusPublished - 29 Jan 2018
Event2017 International Workshop on Big Data and Information Security, WBIS 2017 - Jakarta, Indonesia
Duration: 23 Sep 201724 Sep 2017

Publication series

NameProceedings - WBIS 2017: 2017 International Workshop on Big Data and Information Security
Volume2018-January

Conference

Conference2017 International Workshop on Big Data and Information Security, WBIS 2017
CountryIndonesia
CityJakarta
Period23/09/1724/09/17

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    Wardhana, Y., Putra, H. S., Sakinah, S. I., Jatmiko, W., Mursanto, P., & Setia, P. K. (2018). Block and booth floating point number multiplication algorithms in FPGA's generalized learning vector quantization implementation. In Proceedings - WBIS 2017: 2017 International Workshop on Big Data and Information Security (pp. 69-75). (Proceedings - WBIS 2017: 2017 International Workshop on Big Data and Information Security; Vol. 2018-January). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/IWBIS.2017.8275105