Block and booth floating point number multiplication algorithms in FPGA's generalized learning vector quantization implementation

Yulistiyan Wardhana; H. S. Putra; S. I. Sakinah; Wisnu Jatmiko; Petrus Mursanto; Prahesa Kusuma Setia

doi:10.1109/IWBIS.2017.8275105

Block and booth floating point number multiplication algorithms in FPGA's generalized learning vector quantization implementation

Yulistiyan Wardhana, H. S. Putra, S. I. Sakinah, Wisnu Jatmiko, Petrus Mursanto, Prahesa Kusuma Setia

Department of Computer Science

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

Abstract

Nowadays, smart devices have been rapidly developed. Most of them are just sensors and actuators without independent computation ability. The devices computation would be done in a device coordinator which need communication time between them. It makes the devices can't respond its input in the right time. Independent computation ability is needed by smart devices. Yet, its implementation has limitation in resource usage and accuracy. One of the problem for the devices accuracy is its number representation for its learning implementation. In this research we propose block and booth floating point number implementation to increase smart devices accuracy with their resource usage comparison. The research resulted FPGA components which could improve previous implemented FPGA algorithm accuracy by 17 % with two alternatives: component with minimal time consumption or component with minimal resource consumption.

Original language	English
Title of host publication	Proceedings - WBIS 2017
Subtitle of host publication	2017 International Workshop on Big Data and Information Security
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	69-75
Number of pages	7
ISBN (Electronic)	9781538620380
DOIs	https://doi.org/10.1109/IWBIS.2017.8275105
Publication status	Published - 29 Jan 2018
Event	2017 International Workshop on Big Data and Information Security, WBIS 2017 - Jakarta, Indonesia Duration: 23 Sept 2017 → 24 Sept 2017

Publication series

Name	Proceedings - WBIS 2017: 2017 International Workshop on Big Data and Information Security
Volume	2018-January

Conference

Conference	2017 International Workshop on Big Data and Information Security, WBIS 2017
Country/Territory	Indonesia
City	Jakarta
Period	23/09/17 → 24/09/17

Access to Document

10.1109/IWBIS.2017.8275105

Cite this

Wardhana, Y., Putra, H. S., Sakinah, S. I., Jatmiko, W., Mursanto, P., & Setia, P. K. (2018). Block and booth floating point number multiplication algorithms in FPGA's generalized learning vector quantization implementation. In Proceedings - WBIS 2017: 2017 International Workshop on Big Data and Information Security (pp. 69-75). (Proceedings - WBIS 2017: 2017 International Workshop on Big Data and Information Security; Vol. 2018-January). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/IWBIS.2017.8275105

Wardhana, Yulistiyan ; Putra, H. S. ; Sakinah, S. I. et al. / Block and booth floating point number multiplication algorithms in FPGA's generalized learning vector quantization implementation. Proceedings - WBIS 2017: 2017 International Workshop on Big Data and Information Security. Institute of Electrical and Electronics Engineers Inc., 2018. pp. 69-75 (Proceedings - WBIS 2017: 2017 International Workshop on Big Data and Information Security).

@inproceedings{ec1a285d83ea4cd682d65531ba06d829,

title = "Block and booth floating point number multiplication algorithms in FPGA's generalized learning vector quantization implementation",

abstract = "Nowadays, smart devices have been rapidly developed. Most of them are just sensors and actuators without independent computation ability. The devices computation would be done in a device coordinator which need communication time between them. It makes the devices can't respond its input in the right time. Independent computation ability is needed by smart devices. Yet, its implementation has limitation in resource usage and accuracy. One of the problem for the devices accuracy is its number representation for its learning implementation. In this research we propose block and booth floating point number implementation to increase smart devices accuracy with their resource usage comparison. The research resulted FPGA components which could improve previous implemented FPGA algorithm accuracy by 17 % with two alternatives: component with minimal time consumption or component with minimal resource consumption.",

author = "Yulistiyan Wardhana and Putra, {H. S.} and Sakinah, {S. I.} and Wisnu Jatmiko and Petrus Mursanto and Setia, {Prahesa Kusuma}",

note = "Publisher Copyright: {\textcopyright} 2017 IEEE.; 2017 International Workshop on Big Data and Information Security, WBIS 2017 ; Conference date: 23-09-2017 Through 24-09-2017",

year = "2018",

month = jan,

day = "29",

doi = "10.1109/IWBIS.2017.8275105",

language = "English",

series = "Proceedings - WBIS 2017: 2017 International Workshop on Big Data and Information Security",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

pages = "69--75",

booktitle = "Proceedings - WBIS 2017",

address = "United States",

}

Wardhana, Y, Putra, HS, Sakinah, SI, Jatmiko, W , Mursanto, P & Setia, PK 2018, Block and booth floating point number multiplication algorithms in FPGA's generalized learning vector quantization implementation. in Proceedings - WBIS 2017: 2017 International Workshop on Big Data and Information Security. Proceedings - WBIS 2017: 2017 International Workshop on Big Data and Information Security, vol. 2018-January, Institute of Electrical and Electronics Engineers Inc., pp. 69-75, 2017 International Workshop on Big Data and Information Security, WBIS 2017, Jakarta, Indonesia, 23/09/17. https://doi.org/10.1109/IWBIS.2017.8275105

Block and booth floating point number multiplication algorithms in FPGA's generalized learning vector quantization implementation. / Wardhana, Yulistiyan; Putra, H. S.; Sakinah, S. I. et al.

Proceedings - WBIS 2017: 2017 International Workshop on Big Data and Information Security. Institute of Electrical and Electronics Engineers Inc., 2018. p. 69-75 (Proceedings - WBIS 2017: 2017 International Workshop on Big Data and Information Security; Vol. 2018-January).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - Block and booth floating point number multiplication algorithms in FPGA's generalized learning vector quantization implementation

AU - Wardhana, Yulistiyan

AU - Putra, H. S.

AU - Sakinah, S. I.

AU - Jatmiko, Wisnu

AU - Mursanto, Petrus

AU - Setia, Prahesa Kusuma

PY - 2018/1/29

Y1 - 2018/1/29

N2 - Nowadays, smart devices have been rapidly developed. Most of them are just sensors and actuators without independent computation ability. The devices computation would be done in a device coordinator which need communication time between them. It makes the devices can't respond its input in the right time. Independent computation ability is needed by smart devices. Yet, its implementation has limitation in resource usage and accuracy. One of the problem for the devices accuracy is its number representation for its learning implementation. In this research we propose block and booth floating point number implementation to increase smart devices accuracy with their resource usage comparison. The research resulted FPGA components which could improve previous implemented FPGA algorithm accuracy by 17 % with two alternatives: component with minimal time consumption or component with minimal resource consumption.

AB - Nowadays, smart devices have been rapidly developed. Most of them are just sensors and actuators without independent computation ability. The devices computation would be done in a device coordinator which need communication time between them. It makes the devices can't respond its input in the right time. Independent computation ability is needed by smart devices. Yet, its implementation has limitation in resource usage and accuracy. One of the problem for the devices accuracy is its number representation for its learning implementation. In this research we propose block and booth floating point number implementation to increase smart devices accuracy with their resource usage comparison. The research resulted FPGA components which could improve previous implemented FPGA algorithm accuracy by 17 % with two alternatives: component with minimal time consumption or component with minimal resource consumption.

UR - http://www.scopus.com/inward/record.url?scp=85050761580&partnerID=8YFLogxK

U2 - 10.1109/IWBIS.2017.8275105

DO - 10.1109/IWBIS.2017.8275105

M3 - Conference contribution

AN - SCOPUS:85050761580

T3 - Proceedings - WBIS 2017: 2017 International Workshop on Big Data and Information Security

SP - 69

EP - 75

BT - Proceedings - WBIS 2017

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 2017 International Workshop on Big Data and Information Security, WBIS 2017

Y2 - 23 September 2017 through 24 September 2017

ER -

Wardhana Y, Putra HS, Sakinah SI, Jatmiko W , Mursanto P, Setia PK. Block and booth floating point number multiplication algorithms in FPGA's generalized learning vector quantization implementation. In Proceedings - WBIS 2017: 2017 International Workshop on Big Data and Information Security. Institute of Electrical and Electronics Engineers Inc. 2018. p. 69-75. (Proceedings - WBIS 2017: 2017 International Workshop on Big Data and Information Security). doi: 10.1109/IWBIS.2017.8275105

Block and booth floating point number multiplication algorithms in FPGA's generalized learning vector quantization implementation

Abstract

Publication series

Conference

Access to Document

Other files and links

Fingerprint

Cite this